BUFFER Gate myHDL PYNQZ1

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AND Gate myHDL PYNQZ1AND Gate myHDL PYNQZ1
XORGate myHDL PYNQZ1XORGate myHDL PYNQZ1
NOT Gate myHDL PYNQZ1NOT Gate myHDL PYNQZ1
OR Gate myHDL PYNQZ1OR Gate myHDL PYNQZ1
XNOR Gate myHDL PYNQZ1XNOR Gate myHDL PYNQZ1
NOR Gate myHDL PYNQZ1NOR Gate myHDL PYNQZ1
myHDL 1:4 DEMUX via behavioral using bit vectors on the PYNQ-Z1 (non SoC)myHDL 1:4 DEMUX via behavioral using bit vectors on the PYNQ-Z1 (non SoC)
myHDL 4:1 MUX via MUX stacking 2:1MUXs on PYNQ-Z1 (non SoC)myHDL 4:1 MUX via MUX stacking 2:1MUXs on PYNQ-Z1 (non SoC)